/*
 * Copyright (C) 2015 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-06-09 10:08:26
 *
 */


#ifndef PUB_APB_H
#define PUB_APB_H

#define CTL_BASE_PUB_APB 0x300E0000


#define REG_PUB_APB_BUSMON_CNT_START                  ( CTL_BASE_PUB_APB + 0x0000 )
#define REG_PUB_APB_BUSMON_CFG                        ( CTL_BASE_PUB_APB + 0x0004 )
#define REG_PUB_APB_DDR_EB                            ( CTL_BASE_PUB_APB + 0x0008 )
#define REG_PUB_APB_DDR_SOFT_RST                      ( CTL_BASE_PUB_APB + 0x000C )
#define REG_PUB_APB_DMC_PORT_REMAP_EN                 ( CTL_BASE_PUB_APB + 0x3000 )
#define REG_PUB_APB_DMC_PORTS_MPU_EN                  ( CTL_BASE_PUB_APB + 0x3004 )
#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3008 )
#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x300C )
#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3010 )
#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3014 )
#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3018 )
#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x301C )
#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3020 )
#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3024 )
#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x3028 )
#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP_0            ( CTL_BASE_PUB_APB + 0x302C )
#define REG_PUB_APB_DMC_PORT0_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3030 )
#define REG_PUB_APB_DMC_PORT1_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3034 )
#define REG_PUB_APB_DMC_PORT2_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3038 )
#define REG_PUB_APB_DMC_PORT3_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x303C )
#define REG_PUB_APB_DMC_PORT4_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3040 )
#define REG_PUB_APB_DMC_PORT5_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3044 )
#define REG_PUB_APB_DMC_PORT6_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3048 )
#define REG_PUB_APB_DMC_PORT7_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3050 )
#define REG_PUB_APB_DMC_PORT8_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3054 )
#define REG_PUB_APB_DMC_PORT9_MPU_RANGE               ( CTL_BASE_PUB_APB + 0x3058 )
#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x305C )
#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3060 )
#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3064 )
#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3068 )
#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x306C )
#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3070 )
#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3074 )
#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3078 )
#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x307C )
#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR               ( CTL_BASE_PUB_APB + 0x3080 )
#define REG_PUB_APB_SYS_ENDIAN_CTRL                   ( CTL_BASE_PUB_APB + 0x3090 )
#define REG_PUB_APB_DMC_DUMMY_REG0                    ( CTL_BASE_PUB_APB + 0x30A0 )
#define REG_PUB_APB_DMC_DUMMY_REG1                    ( CTL_BASE_PUB_APB + 0x30A4 )
#define REG_PUB_APB_DMC_DUMMY_REG2                    ( CTL_BASE_PUB_APB + 0x30A8 )
#define REG_PUB_APB_DMC_DUMMY_REG3                    ( CTL_BASE_PUB_APB + 0x30AC )
#define REG_PUB_APB_DMC_QOS_SEL                       ( CTL_BASE_PUB_APB + 0x3100 )
#define REG_PUB_APB_DMC_ARQOS_0_7                     ( CTL_BASE_PUB_APB + 0x3110 )
#define REG_PUB_APB_DMC_ARQOS_8                       ( CTL_BASE_PUB_APB + 0x3114 )
#define REG_PUB_APB_DMC_AWQOS_0_7                     ( CTL_BASE_PUB_APB + 0x3118 )
#define REG_PUB_APB_DMC_AWQOS_8                       ( CTL_BASE_PUB_APB + 0x311C )
#define REG_PUB_APB_DMC_ARQOS_0_ID                    ( CTL_BASE_PUB_APB + 0x3120 )
#define REG_PUB_APB_DMC_ARQOS_1_ID                    ( CTL_BASE_PUB_APB + 0x3124 )
#define REG_PUB_APB_DMC_ARQOS_2_ID                    ( CTL_BASE_PUB_APB + 0x3128 )
#define REG_PUB_APB_DMC_ARQOS_3_ID                    ( CTL_BASE_PUB_APB + 0x312C )
#define REG_PUB_APB_DMC_ARQOS_4_ID                    ( CTL_BASE_PUB_APB + 0x3130 )
#define REG_PUB_APB_DMC_ARQOS_5_ID                    ( CTL_BASE_PUB_APB + 0x3134 )
#define REG_PUB_APB_DMC_ARQOS_6_ID                    ( CTL_BASE_PUB_APB + 0x3138 )
#define REG_PUB_APB_DMC_ARQOS_7_ID                    ( CTL_BASE_PUB_APB + 0x313C )
#define REG_PUB_APB_DMC_ARQOS_8_ID                    ( CTL_BASE_PUB_APB + 0x3140 )
#define REG_PUB_APB_DMC_AWQOS_0_ID                    ( CTL_BASE_PUB_APB + 0x3150 )
#define REG_PUB_APB_DMC_AWQOS_1_ID                    ( CTL_BASE_PUB_APB + 0x3154 )
#define REG_PUB_APB_DMC_AWQOS_2_ID                    ( CTL_BASE_PUB_APB + 0x3158 )
#define REG_PUB_APB_DMC_AWQOS_3_ID                    ( CTL_BASE_PUB_APB + 0x315C )
#define REG_PUB_APB_DMC_AWQOS_4_ID                    ( CTL_BASE_PUB_APB + 0x3160 )
#define REG_PUB_APB_DMC_AWQOS_5_ID                    ( CTL_BASE_PUB_APB + 0x3164 )
#define REG_PUB_APB_DMC_AWQOS_6_ID                    ( CTL_BASE_PUB_APB + 0x3168 )
#define REG_PUB_APB_DMC_AWQOS_7_ID                    ( CTL_BASE_PUB_APB + 0x316C )
#define REG_PUB_APB_DMC_AWQOS_8_ID                    ( CTL_BASE_PUB_APB + 0x3170 )
#define REG_PUB_APB_DMC_EXT_LPCTRL_CFG                ( CTL_BASE_PUB_APB + 0x31A0 )
#define REG_PUB_APB_DMC_EXT_LPCTRL_SEQL               ( CTL_BASE_PUB_APB + 0x31A4 )
#define REG_PUB_APB_DMC_EXT_LPCTRL_SEQH               ( CTL_BASE_PUB_APB + 0x31A8 )
#define REG_PUB_APB_DMC_EXT_LPCTRL_STEP               ( CTL_BASE_PUB_APB + 0x31AC )
#define REG_PUB_APB_QOS_SELECT                        ( CTL_BASE_PUB_APB + 0x31B0 )
#define REG_PUB_APB_DMC_PORTS_MPU_SEL                 ( CTL_BASE_PUB_APB + 0x31B4 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_SEL          ( CTL_BASE_PUB_APB + 0x31B8 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_RID_MASK     ( CTL_BASE_PUB_APB + 0x31BC )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_WID_MASK     ( CTL_BASE_PUB_APB + 0x31C0 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_RID_VAL      ( CTL_BASE_PUB_APB + 0x31C4 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_WID_VAL      ( CTL_BASE_PUB_APB + 0x31C8 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_RHIGH_RANGE  ( CTL_BASE_PUB_APB + 0x31CC )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_RLOW_RANGE   ( CTL_BASE_PUB_APB + 0x31D0 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_WHIGH_RANGE  ( CTL_BASE_PUB_APB + 0x31D4 )
#define REG_PUB_APB_DMC_PORTS_MPU_SHARED_WLOW_RANGE   ( CTL_BASE_PUB_APB + 0x31D8 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH0_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31DC )
#define REG_PUB_APB_DMC_PORTS_MPU_CH0_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31E0 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH1_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31E4 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH1_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31E8 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH2_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31EC )
#define REG_PUB_APB_DMC_PORTS_MPU_CH2_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31F0 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH3_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31F4 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH3_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31F8 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH4_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x31FC )
#define REG_PUB_APB_DMC_PORTS_MPU_CH4_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x3200 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH5_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x3204 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH5_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x3208 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH6_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x320C )
#define REG_PUB_APB_DMC_PORTS_MPU_CH6_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x3210 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH7_RID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x3214 )
#define REG_PUB_APB_DMC_PORTS_MPU_CH7_WID_MASK_VAL    ( CTL_BASE_PUB_APB + 0x3218 )
#define REG_PUB_APB_DMC_PORT_MPU_CH0_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x321C )
#define REG_PUB_APB_DMC_PORT_MPU_CH0_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3220 )
#define REG_PUB_APB_DMC_PORT_MPU_CH1_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3224 )
#define REG_PUB_APB_DMC_PORT_MPU_CH1_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3228 )
#define REG_PUB_APB_DMC_PORT_MPU_CH2_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x322C )
#define REG_PUB_APB_DMC_PORT_MPU_CH2_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3230 )
#define REG_PUB_APB_DMC_PORT_MPU_CH3_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3234 )
#define REG_PUB_APB_DMC_PORT_MPU_CH3_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3238 )
#define REG_PUB_APB_DMC_PORT_MPU_CH4_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x323C )
#define REG_PUB_APB_DMC_PORT_MPU_CH4_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3240 )
#define REG_PUB_APB_DMC_PORT_MPU_CH5_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3244 )
#define REG_PUB_APB_DMC_PORT_MPU_CH5_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3248 )
#define REG_PUB_APB_DMC_PORT_MPU_CH6_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x324C )
#define REG_PUB_APB_DMC_PORT_MPU_CH6_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3250 )
#define REG_PUB_APB_DMC_PORT_MPU_CH7_RLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3254 )
#define REG_PUB_APB_DMC_PORT_MPU_CH7_WLOW_RANGE       ( CTL_BASE_PUB_APB + 0x3258 )
#define REG_PUB_APB_DMC_PORT_MPU_CH0_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x325C )
#define REG_PUB_APB_DMC_PORT_MPU_CH0_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3260 )
#define REG_PUB_APB_DMC_PORT_MPU_CH1_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3264 )
#define REG_PUB_APB_DMC_PORT_MPU_CH1_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3268 )
#define REG_PUB_APB_DMC_PORT_MPU_CH2_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x326C )
#define REG_PUB_APB_DMC_PORT_MPU_CH2_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3270 )
#define REG_PUB_APB_DMC_PORT_MPU_CH3_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3274 )
#define REG_PUB_APB_DMC_PORT_MPU_CH3_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3278 )
#define REG_PUB_APB_DMC_PORT_MPU_CH4_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x327C )
#define REG_PUB_APB_DMC_PORT_MPU_CH4_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3280 )
#define REG_PUB_APB_DMC_PORT_MPU_CH5_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3284 )
#define REG_PUB_APB_DMC_PORT_MPU_CH5_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3288 )
#define REG_PUB_APB_DMC_PORT_MPU_CH6_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x328C )
#define REG_PUB_APB_DMC_PORT_MPU_CH6_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3290 )
#define REG_PUB_APB_DMC_PORT_MPU_CH7_RHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3294 )
#define REG_PUB_APB_DMC_PORT_MPU_CH7_WHIGH_RANGE      ( CTL_BASE_PUB_APB + 0x3298 )
#define REG_PUB_APB_DMC_MPU_VIO_ADDR                  ( CTL_BASE_PUB_APB + 0x329C )
#define REG_PUB_APB_DMC_MPU_VIO_CMD                   ( CTL_BASE_PUB_APB + 0x32A0 )
#define REG_PUB_APB_DMC_MPU_VIO_USERID                ( CTL_BASE_PUB_APB + 0x32A4 )
#define REG_PUB_APB_DMC_REMAP_EN                      ( CTL_BASE_PUB_APB + 0x32A8 )
#define REG_PUB_APB_DMC_PORT0_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32AC )
#define REG_PUB_APB_DMC_PORT0_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32B0 )
#define REG_PUB_APB_DMC_PORT1_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32B4 )
#define REG_PUB_APB_DMC_PORT1_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32B8 )
#define REG_PUB_APB_DMC_PORT2_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32BC )
#define REG_PUB_APB_DMC_PORT2_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32C0 )
#define REG_PUB_APB_DMC_PORT3_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32C4 )
#define REG_PUB_APB_DMC_PORT3_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32C8 )
#define REG_PUB_APB_DMC_PORT4_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32CC )
#define REG_PUB_APB_DMC_PORT4_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32D0 )
#define REG_PUB_APB_DMC_PORT5_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32D4 )
#define REG_PUB_APB_DMC_PORT5_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32D8 )
#define REG_PUB_APB_DMC_PORT6_REMAP_ADDR_0            ( CTL_BASE_PUB_APB + 0x32DC )
#define REG_PUB_APB_DMC_PORT6_REMAP_ADDR_1            ( CTL_BASE_PUB_APB + 0x32E0 )
#define REG_PUB_APB_DMC_MPU_DUMP_ADDR                 ( CTL_BASE_PUB_APB + 0x32E4 )
#define REG_PUB_APB_PUB_DMC_MPU_INT                   ( CTL_BASE_PUB_APB + 0x32E8 )
#define REG_PUB_APB_PUB_AXI_QOS_REG                   ( CTL_BASE_PUB_APB + 0x32EC )
#define REG_PUB_APB_DFS_INT_CTRL                      ( CTL_BASE_PUB_APB + 0x32F0 )
#define REG_PUB_APB_DFS_STATUS                        ( CTL_BASE_PUB_APB + 0x32F4 )
#define REG_PUB_APB_DFS_SW_CTRL                       ( CTL_BASE_PUB_APB + 0x32F8 )
#define REG_PUB_APB_DFS_FC_REQ_DELAY                  ( CTL_BASE_PUB_APB + 0x32FC )
#define REG_PUB_APB_DFS_HW_CTRL                       ( CTL_BASE_PUB_APB + 0x3300 )
#define REG_PUB_APB_DFS_HW_FRQ_RATIO                  ( CTL_BASE_PUB_APB + 0x3334 )
#define REG_PUB_APB_DFS_PURE_SW_CTRL                  ( CTL_BASE_PUB_APB + 0x3338 )
#define REG_PUB_APB_MEM_FW_INT                        ( CTL_BASE_PUB_APB + 0x333C )
#define REG_PUB_APB_AXI_LPC_CTRL_0                    ( CTL_BASE_PUB_APB + 0x3340 )
#define REG_PUB_APB_AXI_LPC_CTRL_1                    ( CTL_BASE_PUB_APB + 0x3344 )
#define REG_PUB_APB_FENCING_CTRL                      ( CTL_BASE_PUB_APB + 0x3348 )
#define REG_PUB_APB_BASE_ADDR                         ( CTL_BASE_PUB_APB + 0x334C )
#define REG_PUB_APB_WIFI_DFS_CTRL                     ( CTL_BASE_PUB_APB + 0x3350 )
#define REG_PUB_APB_DFS_SW_GFREE_CFG                  ( CTL_BASE_PUB_APB + 0x3354 )

/* REG_PUB_APB_BUSMON_CNT_START */


/* REG_PUB_APB_BUSMON_CFG */

#define BIT_PUB_APB_BUSMON_EB                    BIT(23)
#define BIT_PUB_APB_PUB_BUSMON6_EB               BIT(22)
#define BIT_PUB_APB_PUB_BUSMON5_EB               BIT(21)
#define BIT_PUB_APB_PUB_BUSMON4_EB               BIT(20)
#define BIT_PUB_APB_PUB_BUSMON3_EB               BIT(19)
#define BIT_PUB_APB_PUB_BUSMON2_EB               BIT(18)
#define BIT_PUB_APB_PUB_BUSMON1_EB               BIT(17)
#define BIT_PUB_APB_PUB_BUSMON0_EB               BIT(16)
#define BIT_PUB_APB_BUSMON_SOFT_RST              BIT(7)
#define BIT_PUB_APB_PUB_BUSMON6_SOFT_RST         BIT(6)
#define BIT_PUB_APB_PUB_BUSMON5_SOFT_RST         BIT(5)
#define BIT_PUB_APB_PUB_BUSMON4_SOFT_RST         BIT(4)
#define BIT_PUB_APB_PUB_BUSMON3_SOFT_RST         BIT(3)
#define BIT_PUB_APB_PUB_BUSMON2_SOFT_RST         BIT(2)
#define BIT_PUB_APB_PUB_BUSMON1_SOFT_RST         BIT(1)
#define BIT_PUB_APB_PUB_BUSMON0_SOFT_RST         BIT(0)

/* REG_PUB_APB_DDR_EB */


/* REG_PUB_APB_DDR_SOFT_RST */


/* REG_PUB_APB_DMC_PORT_REMAP_EN */


/* REG_PUB_APB_DMC_PORTS_MPU_EN */


/* REG_PUB_APB_DMC_PORT0_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT1_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT2_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT3_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT4_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT5_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT6_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT7_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT8_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT9_ADDR_REMAP_0 */


/* REG_PUB_APB_DMC_PORT0_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT1_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT2_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT3_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT4_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT5_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT6_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT7_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT8_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT9_MPU_RANGE */


/* REG_PUB_APB_DMC_PORT0_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT1_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT2_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT3_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT4_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT5_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT6_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT7_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT8_DUMP_ADDR */


/* REG_PUB_APB_DMC_PORT9_DUMP_ADDR */


/* REG_PUB_APB_SYS_ENDIAN_CTRL */


/* REG_PUB_APB_DMC_DUMMY_REG0 */

#define BIT_PUB_APB_DMC_DUMMY_REG0(x)            (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_DUMMY_REG1 */

#define BIT_PUB_APB_DMC_DUMMY_REG1(x)            (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_DUMMY_REG2 */

#define BIT_PUB_APB_DMC_DUMMY_REG2(x)            (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_DUMMY_REG3 */

#define BIT_PUB_APB_DMC_DUMMY_REG3(x)            (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_QOS_SEL */


/* REG_PUB_APB_DMC_ARQOS_0_7 */


/* REG_PUB_APB_DMC_ARQOS_8 */


/* REG_PUB_APB_DMC_AWQOS_0_7 */


/* REG_PUB_APB_DMC_AWQOS_8 */


/* REG_PUB_APB_DMC_ARQOS_0_ID */


/* REG_PUB_APB_DMC_ARQOS_1_ID */


/* REG_PUB_APB_DMC_ARQOS_2_ID */


/* REG_PUB_APB_DMC_ARQOS_3_ID */


/* REG_PUB_APB_DMC_ARQOS_4_ID */


/* REG_PUB_APB_DMC_ARQOS_5_ID */


/* REG_PUB_APB_DMC_ARQOS_6_ID */


/* REG_PUB_APB_DMC_ARQOS_7_ID */


/* REG_PUB_APB_DMC_ARQOS_8_ID */


/* REG_PUB_APB_DMC_AWQOS_0_ID */


/* REG_PUB_APB_DMC_AWQOS_1_ID */


/* REG_PUB_APB_DMC_AWQOS_2_ID */


/* REG_PUB_APB_DMC_AWQOS_3_ID */


/* REG_PUB_APB_DMC_AWQOS_4_ID */


/* REG_PUB_APB_DMC_AWQOS_5_ID */


/* REG_PUB_APB_DMC_AWQOS_6_ID */


/* REG_PUB_APB_DMC_AWQOS_7_ID */


/* REG_PUB_APB_DMC_AWQOS_8_ID */


/* REG_PUB_APB_DMC_EXT_LPCTRL_CFG */

#define BIT_PUB_APB_SOFT_CMD_NUM(x)              (((x) & 0x7) << 8)
#define BIT_PUB_APB_SOFT_CMD_FC_SEL(x)           (((x) & 0x3) << 4)
#define BIT_PUB_APB_SOFT_CMD_RESP                BIT(3)
#define BIT_PUB_APB_SOFT_CMD_DONE                BIT(2)
#define BIT_PUB_APB_SOFT_CMD_START               BIT(0)

/* REG_PUB_APB_DMC_EXT_LPCTRL_SEQL */

#define BIT_PUB_APB_SOFT_CMD_SEQL(x)             (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_EXT_LPCTRL_SEQH */

#define BIT_PUB_APB_SOFT_CMD_SEQH(x)             (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_EXT_LPCTRL_STEP */

#define BIT_PUB_APB_SOFT_CMD_STEP(x)             (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_QOS_SELECT */


/* REG_PUB_APB_DMC_PORTS_MPU_SEL */

#define BIT_PUB_APB_USRID_SEL(x)                 (((x) & 0xFF) << 17)
#define BIT_PUB_APB_MPU_SEL(x)                   (((x) & 0xFF) << 9)
#define BIT_PUB_APB_MPU_PORT_EN(x)               (((x) & 0xFF) << 1)
#define BIT_PUB_APB_MPU_EN                       BIT(0)

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_SEL */

#define BIT_PUB_APB_MPU_SHARED_PORT(x)           (((x) & 0xF) << 3)
#define BIT_PUB_APB_MPU_SHARED_USRID_SEL         BIT(2)
#define BIT_PUB_APB_MPU_SHARED_SEL               BIT(1)
#define BIT_PUB_APB_MPU_SHARED_EN                BIT(0)

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_RID_MASK */

#define BIT_PUB_APB_MPU_SHARED_RID_MASK(x)       (((x) & 0xFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_WID_MASK */

#define BIT_PUB_APB_MPU_SHARED_WID_MASK(x)       (((x) & 0xFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_RID_VAL */

#define BIT_PUB_APB_MPU_SHARED_RID_VAL(x)        (((x) & 0xFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_WID_VAL */

#define BIT_PUB_APB_MPU_SHARED_WID_VAL(x)        (((x) & 0xFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_SHARED_RHIGH_RANGE(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_RLOW_RANGE */

#define BIT_PUB_APB_MPU_SHARED_RLOW_RANGE(x)     (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_SHARED_WHIGH_RANGE(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_SHARED_WLOW_RANGE */

#define BIT_PUB_APB_MPU_SHARED_WLOW_RANGE(x)     (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH0_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH0_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH0_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH0_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH1_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH1_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH1_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH1_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH2_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH2_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH2_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH2_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH3_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH3_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH3_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH3_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH4_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH4_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH4_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH4_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH5_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH5_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH5_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH5_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH6_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH6_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH6_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH6_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH7_RID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH7_RID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORTS_MPU_CH7_WID_MASK_VAL */

#define BIT_PUB_APB_MPU_CH7_WID_MASK_VAL(x)      (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH0_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH0_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH0_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH0_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH1_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH1_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH1_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH1_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH2_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH2_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH2_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH2_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH3_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH3_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH3_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH3_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH4_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH4_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH4_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH4_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH5_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH5_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH5_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH5_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH6_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH6_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH6_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH6_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH7_RLOW_RANGE */

#define BIT_PUB_APB_MPU_CH7_RLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH7_WLOW_RANGE */

#define BIT_PUB_APB_MPU_CH7_WLOW_RANGE(x)        (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH0_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH0_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH0_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH0_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH1_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH1_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH1_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH1_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH2_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH2_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH2_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH2_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH3_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH3_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH3_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH3_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH4_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH4_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH4_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH4_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH5_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH5_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH5_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH5_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH6_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH6_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH6_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH6_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH7_RHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH7_RHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT_MPU_CH7_WHIGH_RANGE */

#define BIT_PUB_APB_MPU_CH7_WHIGH_RANGE(x)       (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_MPU_VIO_ADDR */

#define BIT_PUB_APB_DMC_MPU_VIO_ADDR(x)          (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_MPU_VIO_CMD */

#define BIT_PUB_APB_DMC_MPU_VIO_CMD(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_MPU_VIO_USERID */

#define BIT_PUB_APB_DMC_MPU_VIO_USERID(x)        (((x) & 0xFF))

/* REG_PUB_APB_DMC_REMAP_EN */

#define BIT_PUB_APB_DMC_REMAP_EN(x)              (((x) & 0x3FFF))

/* REG_PUB_APB_DMC_PORT0_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT0_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT0_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT0_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT1_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT1_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT1_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT1_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT2_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT2_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT2_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT2_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT3_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT3_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT3_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT3_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT4_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT4_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT4_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT4_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT5_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT5_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT5_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT5_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT6_REMAP_ADDR_0 */

#define BIT_PUB_APB_DMC_PORT6_REMAP_ADDR_0(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_PORT6_REMAP_ADDR_1 */

#define BIT_PUB_APB_DMC_PORT6_REMAP_ADDR_1(x)    (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_DMC_MPU_DUMP_ADDR */

#define BIT_PUB_APB_DMC_MPU_DUMP_ADDR(x)         (((x) & 0xFFFFFFFF))

/* REG_PUB_APB_PUB_DMC_MPU_INT */

#define BIT_PUB_APB_INT_DMC_MPU_VIO              BIT(3)
#define BIT_PUB_APB_DMC_MPU_VIO_INT_RAW          BIT(2)
#define BIT_PUB_APB_DMC_MPU_VIO_INT_CLR          BIT(1)
#define BIT_PUB_APB_DMC_MPU_VIO_INT_EN           BIT(0)

/* REG_PUB_APB_PUB_AXI_QOS_REG */

#define BIT_PUB_APB_AWQOS_THRESHOLD_CP(x)        (((x) & 0xF) << 28)
#define BIT_PUB_APB_ARQOS_THRESHOLD_CP(x)        (((x) & 0xF) << 24)
#define BIT_PUB_APB_AWQOS_THRESHOLD_AON_WCN(x)   (((x) & 0xF) << 20)
#define BIT_PUB_APB_ARQOS_THRESHOLD_AON_WCN(x)   (((x) & 0xF) << 16)
#define BIT_PUB_APB_AWQOS_WCN(x)                 (((x) & 0xF) << 12)
#define BIT_PUB_APB_ARQOS_WCN(x)                 (((x) & 0xF) << 8)
#define BIT_PUB_APB_AWQOS_AON(x)                 (((x) & 0xF) << 4)
#define BIT_PUB_APB_ARQOS_AON(x)                 (((x) & 0xF))

/* REG_PUB_APB_DFS_INT_CTRL */

#define BIT_PUB_APB_DFS_ERROR_INT_CLR            BIT(5)
#define BIT_PUB_APB_DFS_ERROR_INT_EN             BIT(4)
#define BIT_PUB_APB_DFS_COMPLETE_INT_CLR         BIT(3)
#define BIT_PUB_APB_DFS_COMPLETE_INT_EN          BIT(2)
#define BIT_PUB_APB_HW_DFS_EXIT_INT_CLR          BIT(1)
#define BIT_PUB_APB_HW_DFS_EXIT_INT_EN           BIT(0)

/* REG_PUB_APB_DFS_STATUS */

#define BIT_PUB_APB_HW_DFS_FSM_STATE(x)          (((x) & 0xF) << 7)
#define BIT_PUB_APB_HW_DFS_FSM_IDLE              BIT(6)
#define BIT_PUB_APB_DFS_ERROR_INT_RAW            BIT(5)
#define BIT_PUB_APB_INT_DFS_ERROR                BIT(4)
#define BIT_PUB_APB_DFS_COMPLETE_INT_RAW         BIT(3)
#define BIT_PUB_APB_INT_DFS_COMPLETE             BIT(2)
#define BIT_PUB_APB_HW_DFS_EXIT_INT_RAW          BIT(1)
#define BIT_PUB_APB_INT_HW_DFS_EXIT              BIT(0)

/* REG_PUB_APB_DFS_SW_CTRL */

#define BIT_PUB_APB_PUB_DFS_SW_SWITCH_PERIOD(x)  (((x) & 0xFFF) << 20)
#define BIT_PUB_APB_PUB_DFS_SW_RATIO_DEFAULT(x)  (((x) & 0x7F) << 13)
#define BIT_PUB_APB_PUB_DFS_SW_RATIO(x)          (((x) & 0x7F) << 6)
#define BIT_PUB_APB_PUB_DFS_SW_FRQ_SEL(x)        (((x) & 0x3) << 4)
#define BIT_PUB_APB_PUB_DFS_SW_RESP              BIT(3)
#define BIT_PUB_APB_PUB_DFS_SW_ACK               BIT(2)
#define BIT_PUB_APB_PUB_DFS_SW_REQ               BIT(1)
#define BIT_PUB_APB_PUB_DFS_SW_ENABLE            BIT(0)

/* REG_PUB_APB_DFS_FC_REQ_DELAY */

#define BIT_PUB_APB_DFS_FC_REQ_DELAY(x)          (((x) & 0x7))

/* REG_PUB_APB_DFS_HW_CTRL */


/* REG_PUB_APB_DFS_HW_FRQ_RATIO */


/* REG_PUB_APB_DFS_PURE_SW_CTRL */

#define BIT_PUB_APB_PURE_SW_DFS_ACK              BIT(14)
#define BIT_PUB_APB_PURE_SW_DFS_RESP             BIT(13)
#define BIT_PUB_APB_PURE_SW_DFS_FC_REQ           BIT(12)
#define BIT_PUB_APB_PURE_SW_DFS_REQ              BIT(11)
#define BIT_PUB_APB_PURE_SW_DFS_FC_ACK           BIT(10)
#define BIT_PUB_APB_PURE_SW_DFS_FRQ_SEL(x)       (((x) & 0x3) << 8)
#define BIT_PUB_APB_EMC_CKG_SEL_PURE_SW(x)       (((x) & 0x7F) << 1)
#define BIT_PUB_APB_DFS_SW_DFS_MODE              BIT(0)

/* REG_PUB_APB_MEM_FW_INT */

#define BIT_PUB_APB_MEM_FW_INT_RAW               BIT(3)
#define BIT_PUB_APB_INT_MEM_FW                   BIT(2)
#define BIT_PUB_APB_MEM_FW_INT_CLR               BIT(1)
#define BIT_PUB_APB_MEM_FW_INT_EN                BIT(0)

/* REG_PUB_APB_AXI_LPC_CTRL_0 */

#define BIT_PUB_APB_LP_FORCE_AON_WCN_S0          BIT(11)
#define BIT_PUB_APB_LP_EB_AON_WCN_S0             BIT(10)
#define BIT_PUB_APB_LP_FORCE_AON_WCN_M1          BIT(9)
#define BIT_PUB_APB_LP_EB_AON_WCN_M1             BIT(8)
#define BIT_PUB_APB_LP_FORCE_AON_WCN_M0          BIT(7)
#define BIT_PUB_APB_LP_EB_AON_WCN_M0             BIT(6)
#define BIT_PUB_APB_LP_FORCE_CP_S0               BIT(5)
#define BIT_PUB_APB_LP_EB_CP_S0                  BIT(4)
#define BIT_PUB_APB_LP_FORCE_CP_M1               BIT(3)
#define BIT_PUB_APB_LP_EB_CP_M1                  BIT(2)
#define BIT_PUB_APB_LP_FORCE_CP_M0               BIT(1)
#define BIT_PUB_APB_LP_EB_CP_M0                  BIT(0)

/* REG_PUB_APB_AXI_LPC_CTRL_1 */

#define BIT_PUB_APB_LP_NUM(x)                    (((x) & 0xFFFF))

/* REG_PUB_APB_FENCING_CTRL */

#define BIT_PUB_APB_DDR_FENCING_EN               BIT(30)
#define BIT_PUB_APB_FENCING_CHNL_IDLE_CNT(x)     (((x) & 0x3FFFFFFF))

/* REG_PUB_APB_BASE_ADDR */

#define BIT_PUB_APB_PUB_CP_BASE_ADDR(x)          (((x) & 0xF) << 12)
#define BIT_PUB_APB_WTL_CP_BASE_ADDR(x)          (((x) & 0xF) << 8)
#define BIT_PUB_APB_WCN_BASE_ADDR(x)             (((x) & 0xF) << 4)
#define BIT_PUB_APB_AON_BASE_ADDR(x)             (((x) & 0xF))

/* REG_PUB_APB_WIFI_DFS_CTRL */

#define BIT_PUB_APB_WIFI_DFS_TIMEOUT_FLAG        BIT(23)
#define BIT_PUB_APB_WIFI_DFS_ACK                 BIT(22)
#define BIT_PUB_APB_WIFI_DFS_URGENCY_CTRL_EN     BIT(21)
#define BIT_PUB_APB_WIFI_FIFO_URGENCY_CTRL_EN    BIT(20)
#define BIT_PUB_APB_WIFI_DFS_SW_REQ              BIT(19)
#define BIT_PUB_APB_WIFI_DFS_MODE                BIT(18)
#define BIT_PUB_APB_WIFI_DFS_TIMEOUT_EN          BIT(17)
#define BIT_PUB_APB_WIFI_DFS_TIMEOUT_PERIOD(x)   (((x) & 0xFFFF) << 1)
#define BIT_PUB_APB_WIFI_DFS_HW_BYPASS           BIT(0)

/* REG_PUB_APB_DFS_SW_GFREE_CFG */

#define BIT_PUB_APB_CGM_DFS_GFREE_SWITCH_SW_EN   BIT(24)
#define BIT_PUB_APB_CGM_DFS_GFREE_SWITCH_DIV(x)  (((x) & 0xF) << 20)
#define BIT_PUB_APB_CGM_DFS_GFREE_SWITCH_SEL     BIT(19)
#define BIT_PUB_APB_GFREE_SW_OPEN_DELAY(x)       (((x) & 0x1FF) << 10)
#define BIT_PUB_APB_GFREE_SW_CLOSE_DELAY(x)      (((x) & 0x1FF) << 1)
#define BIT_PUB_APB_GFREE_SW_CTRL_BYPASS         BIT(0)


#endif /* PUB_APB_H */

